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For two-position jumpers (3-post), "RIGHT" is
toward the bracket end of the board; "LEFT" is toward the memory
sockets.
* = default value
(Also refer to JU18 - Combo I/O Reset Connect.)
| INSTALL= |
Connect speaker data signal to pin 8 of Combo I/O connector
(P5A) * |
| REMOVE= |
Disconnect |
INSTALL = Reset to null
REMOVE = Normal operation *
LEFT = Monochrome
RIGHT = Color *
The Flash ROM has two programmable sections: the
Boot Block for "flashing" in the BIOS and the Main Block for the executable
BIOS and PnP parameters. Normally only the Main Block is updated when
a new BIOS is flashed into the system.
|
JU10 |
JU11 |
| Program All (Boot and Main) |
Bottom |
Bottom |
| Normal PnP (Program Main Block) |
Bottom * |
Top * |
| Write Protect |
Top |
Top |
INSTALL = Clear CMOS
REMOVE = Operate *
NOTE: The CMOS Clear jumper works on power-up. To clear the CMOS,
power down the system, install the jumper, then turn the power back
on. CMOS is cleared during the POST routines. Then power down the
system again and remove the jumper before the next power-up.
|
This jumper must be removed (disabled).
INSTALL = Enable 3.3V monitor
REMOVE = Disable monitor *
NOTE: JU15 enables the 3.3V monitor, which monitors the 3.3V power
plane of the backplane. This voltage is routed to the SBC via the
PICMG® connector. The monitor generates a RESET to the SBC if 3.3V
is below tolerance. If your system does not supply 3.3V to
the backplane, this jumper must be removed (disabled).
LEFT = Normal reset *
RIGHT = Enable watchdog
(Also refer to JU7 = Combo I/O Speaker Connect.)
| INSTALL= |
Connect reset data signal to pin 1 of Combo I/O connector
(P5A) * |
| REMOVE= |
Disconnect |
|
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Pin 1 on the connectors is indicated by the square
pad on the PCB.
5 pin single row header, Amp #640456-5
| PIN |
SIGNAL |
| 1 |
LED Power |
| 2 |
Key |
| 3 |
Gnd |
| 4 |
Keylock Data |
| 5 |
Gnd |
34 pin dual row header,
Robinson Nugent #IDH-34LP-S3-TR
| PIN |
SIGNAL |
| 1 |
Gnd |
| 3 |
Gnd |
| 5 |
Gnd |
| 7 |
Gnd |
| 9 |
Gnd |
| 11 |
Gnd |
| 13 |
Gnd |
| 15 |
Gnd |
| 17 |
Gnd |
| 19 |
Gnd |
| 21 |
Gnd |
| 23 |
Gnd |
| 25 |
Gnd |
| 27 |
Gnd |
| 29 |
Gnd |
| 31 |
Gnd |
| 33 |
Gnd |
|
| PIN |
SIGNAL |
| 2 |
N-RPM |
| 4 |
NC |
| 6 |
D-Rate0 |
| 8 |
P-Index |
| 10 |
N-Motoron 1 |
| 12 |
N-Drive Sel2 |
| 14 |
N-Drive Sel1 |
| 16 |
N-Motoron 2 |
| 18 |
N-Dir |
| 20 |
N-Stop Step |
| 22 |
N-Write Data |
| 24 |
N-Write Gate |
| 26 |
P-Track 0 |
| 28 |
P-Write Protect |
| 30 |
N-Read Data |
| 32 |
N-Side Select |
| 34 |
Disk Chng |
|
6 pin mini DIN, Kycon #KMDG-6S-BS-PS
| PIN |
SIGNAL |
| 1 |
Kbd Data |
| 2 |
Reserved |
| 3 |
Gnd |
| 4 |
Kbd Power (+5V fused) with
self-resetting fuse |
| 5 |
Kbd Clock |
| 6 |
Reserved |
5 pin single row header, Amp #640456-5
| PIN |
SIGNAL |
| 1 |
Kbd Clock |
| 2 |
Kbd Data |
| 3 |
Key |
| 4 |
Kbd Gnd |
| 5 |
Kbd Power (+5V fused) with
self-resetting fuse |
4 pin single row header, Amp #640456-4
| PIN |
SIGNAL |
| 1 |
Speaker Data |
| 2 |
Key |
| 3 |
Gnd |
| 4 |
+5V |
8 pin single row header, Amp #640456-8
| PIN |
SIGNAL |
| 1 |
Reset (See JU18 in Configuration
Jumpers above.) |
| 2 |
Gnd |
| 3 |
NC |
| 4 |
Kbd Clock |
| 5 |
Kbd Data |
| 6 |
Kbd Lock Data |
| 7 |
Kbd Power (+5V fused) with
self-resetting fuse |
| 8 |
Speaker Data |
10 pin dual row header, 3M #30310-6002HB
| PIN |
SIGNAL |
| 1 |
Carrier Detect |
| 3 |
Receive Data-I |
| 5 |
Transmit Data-0 |
| 7 |
Data Terminal Ready-0 |
| 9 |
Signal Gnd |
|
| PIN |
SIGNAL |
| 2 |
Data Set Ready-I |
| 4 |
Request to Send-O |
| 6 |
Clear to Send-I |
| 8 |
Ring Indicator-I |
| 10 |
NC |
|
10 pin dual row header, 3M #30310-6002HB
| PIN |
SIGNAL |
| 1 |
Carrier Detect |
| 3 |
Receive Data-I |
| 5 |
Transmit Data-0 |
| 7 |
Data Terminal Ready-0 |
| 9 |
Signal Gnd |
|
| PIN |
SIGNAL |
| 2 |
Data Set Ready-I |
| 4 |
Request to Send-O |
| 6 |
Clear to Send-I |
| 8 |
Ring Indicator-I |
| 10 |
NC |
|
26 pin dual row header, 3M #30326-6002HB
| PIN |
SIGNAL |
| 1 |
Strobe |
| 3 |
Data Bit 0 |
| 5 |
Data Bit 1 |
| 7 |
Data Bit 2 |
| 9 |
Data Bit 3 |
| 11 |
Data Bit 4 |
| 13 |
Data Bit 5 |
| 15 |
Data Bit 6 |
| 17 |
Data Bit 7 |
| 19 |
ACK |
| 21 |
Busy |
| 23 |
Paper End |
| 25 |
Slct |
|
| PIN |
SIGNAL |
| 2 |
Auto Feed XT |
| 4 |
Error |
| 6 |
Init |
| 8 |
Slct In |
| 10 |
Gnd |
| 12 |
Gnd |
| 14 |
Gnd |
| 16 |
Gnd |
| 18 |
Gnd |
| 20 |
Gnd |
| 22 |
Gnd |
| 24 |
Gnd |
| 26 |
NC |
|
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6 pin mini DIN, Kycon #KMDG-6S-BS-PS
| PIN |
SIGNAL |
| 1 |
Ms Data |
| 2 |
Reserved |
| 3 |
Gnd |
| 4 |
Kbd Power (+5V fused) with
self-resetting fuse |
| 5 |
Ms Clock |
| 6 |
Reserved |
6 pin single row header, Amp #640456-6
| PIN |
SIGNAL |
| 1 |
Ms Data |
| 2 |
Reserved |
| 3 |
Kbd Gnd |
| 4 |
Kbd Power (+5V fused) with
self-resetting fuse |
| 5 |
Ms Clock |
| 6 |
Reserved |
2 pin header, Amp #640456-2
| PIN |
SIGNAL |
| 1 |
Negative External Reset |
| 2 |
Gnd |
40 pin dual row header,
Robinson Nugent #IDH-40LP-S3-TR
| PIN |
SIGNAL |
| 1 |
Reset |
| 3 |
Data 7 |
| 5 |
Data 6 |
| 7 |
Data 5 |
| 9 |
Data 4 |
| 11 |
Data 3 |
| 13 |
Data 2 |
| 15 |
Data 1 |
| 17 |
Data 0 |
| 19 |
Gnd |
| 21 |
DRQ 0 |
| 23 |
IOW |
| 25 |
IOR |
| 27 |
IORDY |
| 29 |
DACK 0 |
| 31 |
IRQ 14 |
| 33 |
Add 1 |
| 35 |
Add 0 |
| 37 |
CS 1P |
| 39 |
IDEACTP |
|
| PIN |
SIGNAL |
| 2 |
Gnd |
| 4 |
Data 8 |
| 6 |
Data 9 |
| 8 |
Data 10 |
| 10 |
Data 11 |
| 12 |
Data 12 |
| 14 |
Data 13 |
| 16 |
Data 14 |
| 18 |
Data 15 |
| 20 |
NC |
| 22 |
Gnd |
| 24 |
Gnd |
| 26 |
Gnd |
| 28 |
+5V |
| 30 |
Gnd |
| 32 |
IOCS16 |
| 34 |
Gnd |
| 36 |
Add 2 |
| 38 |
CS 3P |
| 40 |
Gnd |
|
40 pin dual row header,
Robinson Nugent #IDH-40LP-S3-TR
| PIN |
SIGNAL |
| 1 |
Reset |
| 3 |
Data 7 |
| 5 |
Data 6 |
| 7 |
Data 5 |
| 9 |
Data 4 |
| 11 |
Data 3 |
| 13 |
Data 2 |
| 15 |
Data 1 |
| 17 |
Data 0 |
| 19 |
Gnd |
| 21 |
DRQ 1 |
| 23 |
IOW |
| 25 |
IOR |
| 27 |
IORDY |
| 29 |
DACK 1 |
| 31 |
MIRQ 0 |
| 33 |
Add 1 |
| 35 |
Add 0 |
| 37 |
CS 1S |
| 39 |
IDEACTS |
|
| PIN |
SIGNAL |
| 2 |
Gnd |
| 4 |
Data 8 |
| 6 |
Data 9 |
| 8 |
Data 10 |
| 10 |
Data 11 |
| 12 |
Data 12 |
| 14 |
Data 13 |
| 16 |
Data 14 |
| 18 |
Data 15 |
| 20 |
NC |
| 22 |
Gnd |
| 24 |
Gnd |
| 26 |
Gnd |
| 28 |
+5V |
| 30 |
Gnd |
| 32 |
IOCS16 |
| 34 |
Gnd |
| 36 |
Add 2 |
| 38 |
CS 3S |
| 40 |
Gnd |
|
4 pin single row header, Amp #640456-4
(This connector is used for both IDE and SCSI drives. See JU19 in
the Jumpers section.)
| PIN |
SIGNAL |
| 1 |
+5V Pullup |
| 2 |
Light |
| 3 |
Light |
| 4 |
+5V Pullup |
8 pin dual row header, Molex #702-46-0821
(+5V fused with self-resetting fuses)
| PIN |
SIGNAL |
| 1 |
+5V - USB0 |
| 3 |
USB0- |
| 5 |
USB0+ |
| 7 |
Gnd - USB0 |
|
| PIN |
SIGNAL |
| 2 |
+5V - USB1 |
| 4 |
USB1- |
| 6 |
USB1+ |
| 8 |
Gnd - USB1 |
|
6 pin single row header, Amp #640456-6
| PIN |
SIGNAL |
| 1 |
Gnd |
| 2 |
GPO (General Purpose Output) |
| 3 |
CI (Chassis Intrusion Input) |
| 4 |
FAN1 (Fan 1 Tachometer Input) |
| 5 |
FAN2 (Fan 2 Tachometer Input) |
| 6 |
OS# (Temperature Sense Output) |
3 pin single row header, Molex #22-23-2031
| PIN |
SIGNAL |
| 1 |
Gnd |
| 2 |
+12V |
| 3 |
FanTach |
|
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The
DRAM interface consists of two dual in-line memory module (DIMM)
sockets and supports auto detection of memory up to 512MB of Synchronous
DRAM (SDRAM). Minimum memory size is 8MB. The System BIOS automatically
detects memory type, size and speed.
The SBC uses industry standard 64-bit or 72-bit
wide gold finger DIMM DRAM in two 168-pin DIMM sockets.
Memory can
be installed in one or both DIMM sockets. If only one DIMM module
is used, it must be populated in the top DIMM socket (Bank 1 - BK1).
If two modules are used, they must be the same DIMM type, but may
be different sizes (see table below). EDO DIMMs are not supported.
All DIMMs must have gold contacts.
The SBC supports DIMM memory modules which are
PC-100 compliant and have the following features:
- 168-pin DIMMs with gold-plated contacts
- 100MHz SDRAM
- Non-ECC (64-bit) or ECC (72-bit) memory
- 3.3 volt only
- Single or double-sided DIMMs in the sizes listed below
- Buffered or Registered configuration
| DIMM Size |
DIMM Type |
Non-ECC |
ECC |
| 8 MB |
Unbuffered |
1M x 64 |
1M x 72 |
| 16 MB |
Unbuffered |
2M x 64 |
2M x 72 |
| 32 MB |
Unbuffered |
4M x 64 |
4M x 72 |
| 64 MB |
Unbuffered |
8M x 64 |
8M x 72 |
| 128 MB |
Unbuffered |
16M x 64 |
16M x 72 |
| 256 MB |
Registered |
32M x 64 |
32M x 72 |
All memory components and DIMMs used with the
SBC must be PC-100 compliant, which means that they comply with
Intel's PC SDRAM specifications. These include the PC SDRAM Specification
(memory component specific), the PC Unbuffered DIMM Specification,
the PC Registered DIMM Specification and the PC Serial Presence
Detect Specification. The PC SDRAM specifications can be found at
Intel's Developer's web site at http://developer.intel.com/design/pcisets/memory.
* Intel and Pentium are registered trademarks
and Celeron is a trademark of Intel Corporation.
All other product names are trademarks of
their respective owners.
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