Provides eleven PCI Local Bus slots which support
PCI Local Bus option cards; seven of these PCI slots also support
PCI-X option cards, which must be either +3.3V or universal option
cards. The backplane's PCI-X bridges automatically detect the
following option card parameters:
Option card type -- PCI or PCI-X
Architecture -- 32-bit or 64-bit
Bus speed -- 33MHz, 66MHz, 100MHz, or 133MHz
The backplane also determines the speed at which the segment is
capable of running without violating loading specifications. The
auto-detection feature helps ensure stable system behavior and
prevents board damage.
Accepts a PICMG® 1.0 compliant processor. The
backplane supports new PCI-X compatible processors and legacy
processors that support +3.3V signaling. Trenton's XPT single
board computer is an example of a processor or SBC that is PCI-X
compatible; Trenton's SLE, ULE and XPI are legacy SBCs that support
+3.3V signaling.
The backplane is an eight-layer, .062" thick
board with three separate signal layers: +5V, +3.3V and ground.
Multi-layer backplane construction provides excellent noise immunity.
The power indicators provide a convenient visual
check for +5V, -5V, +12V, -12V and +3.3V power connections.
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The standard AT power connection is available
through a 12-pin .156 MTA connector. Power connection for +3.3V
is available through a 12-pin .156 MTA connector or an ATX connector
(optional).
Additional power capacity is available through
a .156 MTA connector.
Optional extended-current connectors provide
additional power capacity for power-intensive applications --
up to 60 Amps of +5V plus 60 Amps of +3.3V.
The PCI-to-PCI bridge supports the PCI Local
Bus 2.1 specification. The BP1/1/2/4/4 backplane has bus mastering
capabilities on all four PCI Local Bus Slots.
The PCI-X-to-PCI-X bridge eases the transition
to PCI-X by supporting the PCI Local Bus as well as enabling 64-bit
PCI-X architectures capable of running at speeds up to 133MHz
at transfer rates up to 1GB/s. The bridge chip allows concurrent
operations on both buses and is fully compliant with the PCI-X
Addendum to the PCI Local Bus Specifications Revision 1.0 and
the PCI Local Bus Specification 2.1. |